Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
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United States of America Patent
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Nov 25, 1997
Grant Date -
N/A
app pub date -
Aug 19, 1996
filing date -
Jul 31, 1992
priority date (Note) -
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Abstract
An apparatus and method for improving the performance of pipelined computer processors which have segment bits for specifying the operand size, the address size for memory reference, and the stack size, and which can run self-modifying code. The processor predicts segment bits based on previously used segment bits. Actual segment bits are later determined during execution of an instruction. The predicted segment bits are compared with the actual segment bits, and the pipeline is flushed if they do not match. Also, an instruction verification method is provided to determine if self-modifying code has modified instructions already in the pipeline. Upon execution of a write instruction, each instruction address in the pipeline is compared with the write address. If a match is found, the pipeline is flushed.
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