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Abstract

A ROM device with a 3-dimensional memory cell structure that allows a high packing density of memory cells in the ROM device. The ROM device includes a silicon substrate having a plurality of parallel trenches formed thereon. These trenches define mesa regions therebetween. Source/drain regions are then formed on the trenches and the mesa regions. Sidewall spacers are formed on lateral sides of selected trenches. A gate oxide layer is then formed over the silicon substrate. Gate layers are then formed on the gate oxide layers along a direction perpendicular to the trenches. These gate layers serve as word lines. The bit lines over the trenches and the mesa regions utilize channel areas between each neighboring pair of source/drain regions in the horizontal direction to define a plurality of horizontal memory cells at intersections with the word lines. Each horizontal memory cell can be programmed by ion implantation. Similarly, the bit lines on lateral sides of the mesa regions utilize channel areas between each neighboring pair of source/drain regions in the vertical direction to define a plurality of vertical memory cells at these intersections. Each vertical memory cell can be programmed by ion implantation.

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First Claim