High speed I.sub.DDQ monitor circuit
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United States of America Patent
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Dec 2, 1997
Issued Date -
N/A
app pub date -
Sep 27, 1996
filing date -
Aug 11, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.
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