Switching control circuitry for low noise CMOS inverter
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United States of America Patent
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Dec 2, 1997
Grant Date -
N/A
app pub date -
Jun 29, 1995
filing date -
Aug 16, 1994
priority date (Note) -
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Abstract
An inverter device is provided which comprises an inverter including a pair of transistors, and first and second delay circuits. The first and second delay circuits are connected to respective inputs of the pair of transistors so as to cause the transistors of the pair to switch with a greater time difference, thereby reducing noise due to switching operations in the inverter.
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