Hardware arrangement of effectively expanding data processing time in pipelining in a microcomputer system and a method thereof
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United States of America Patent
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Dec 2, 1997
Grant Date -
N/A
app pub date -
Sep 24, 1996
filing date -
Jul 2, 1993
priority date (Note) -
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Abstract
A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangment is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.
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