Semiconductor wafers with device protection means and with interconnect lines on scribing lines
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United States of America Patent
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-
Dec 9, 1997
Grant Date -
N/A
app pub date -
Sep 13, 1995
filing date -
Sep 13, 1994
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A manufacturing method for fabricating integrated electronic circuits on a semiconductor support provides a plurality of integrated circuits and provides a plurality of scribing lines. The scribing lines are located such that the electronic circuits are regularly spaced apart by the scribing lines. A network of electrical connection lines is provided in at least one of the scribing lines. Metallization strips are provided in the scribing lines as electrical connection lines, and the electrical connection lines are connected to the integrated circuit. At least one current limitation element is provided between the electrical connection line and the integrated circuit. In this manner it is possible to simultaneously perform electrical testing of all the circuits present on the same wafer.
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