Importance

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Abstract

A software program and method to coordinate with hardware which is capable of dynamic speed switching is used to reset timing (bus and processor clock) sensitive elements such that machine speed (bus and processor clock frequencies) can be changed dynamically without interruption of I/O services or general OS and application level functions. This includes storing timing parameters for different system operating speeds. These timing parameters can be stored, then loaded into low level memory in coordination with certain service and speed changes to effect a smooth speed transition within a minimal number of clock cycles. In a preferred form, this includes examining the hardware configuration at system startup and determining timing parameters for the specific hardware installed in the system.

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First Claim