High-speed solid state buffer circuit and method for producing the same
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United States of America Patent
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Dec 16, 1997
Issued Date -
N/A
app pub date -
Jan 11, 1996
filing date -
Feb 14, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A high-speed solid state buffer circuit and method for producing the same. A buffer circuit accepts logic input signals and transforms the signals to an output signal which can drive a heavy load. By using an output stage pull-up device that includes a parallel combination of an enhancement mode FET and a depletion mode FET, a solid-state buffer circuit with increased speed and output voltage swing is achieved. Most conveniently, the buffer takes the form of a logic inverter. However, the buffer can also be used to form a multiple input NOR gate. The circuit is most suitable for realization in GaAs technology.
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