Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints
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United States of America Patent
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Dec 16, 1997
Grant Date -
N/A
app pub date -
Sep 8, 1995
filing date -
Sep 8, 1995
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Abstract
A process for designing an integrated circuit chip includes specifying a set of cells, a set of wiring nets for interconnecting the cells, and a set of regions on the chip in which the cells are to be placed. An assignment of the cells of the set to the regions is generated, and the set of cells is randomly divided into a first subset of cells which remain in the assignment, and a second subset of cells which are removed from the assignment. Penalties are computed for assigning the cells of the second subset to the regions respectively, and the cells of the second subset are assigned to the regions such that a total penalty thereof is minimized. The process is repeated iteratively with the size of the second subset being progressively reduced relative to the size of the first subset until an end criterion is reached.
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