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Abstract

A clock recovery system and method for maintaining the frequency of a decoder clock at approximately the same frequency as an encoder clock based on program clock reference (PCR) values contained in a digital data stream. A voltage controlled oscillator (78) produces a decoder clock that is divided by a divider (66). The divided decoder clock clocks a 16-bit counter (64) to produce a system time clock (STC). In an exemplary embodiment, the 16-bit counter is constructed of an 8-bit hardware register (82) and an 8-bit software register (84). The 16-bit counter is initially loaded with a PCR value from the digital data stream. As subsequent PCR values are received in the data stream, a 16-bit subtractor (68) subtracts the value of the PCR from the value of the STC to produce an error signal. To produce a control signal the error signal is filtered, scaled, and added to a control variable within a low-pass filter and processor (70). The control signal is applied to the voltage controlled oscillator to adjust the oscillation frequency of the oscillator. A coarse mode of operation quickly adjusts the voltage controlled oscillator frequency, and a fine mode of operation more slowly adjusts the oscillator frequency. The two modes of operation ensure that the frequency of the decoder clock quickly approaches, and is kept approximately the same, as the frequency of the encoder clock.

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First Claim