Routing resources for hierarchical FPGA
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United States of America Patent
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Dec 23, 1997
Grant Date -
N/A
app pub date -
Jun 6, 1995
filing date -
May 2, 1995
priority date (Note) -
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Abstract
In an FPGA having a hierarchical routing structure, additional routing lines are provided which have different destinations for different cells within a block. A pattern is chosen which allows signal lines to turn corners conveniently. In one embodiment having cells arranged into 4.times.4 blocks, cells on the diagonal of a block generate signals which are provided to switches which form one boundary of the block.
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