Importance

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Abstract

A computer system is composed of a processor 10, a memory control circuit 70, and interleaved bank memories 41 through 44. The memory control circuit contains random access queue entries 71 through 73 commonly used by all memories 41 through 44. A bypass 80 allows direct bank access without writing memory access requests to the queue entries 71 through 73. Sequence is maintained by the in-bank access sequence assurance circuits 90. Because the queue entries 71 through 73 allow memory control without providing the number of entries in an integral multiple of the number of banks, the entire circuit scale is reduced. All bank busy circuits in the system are integrated on a single LSI to reduce delay, thereby enhancing processing speed. The bypass 80 eliminates queue read/write cycles from data access time, thereby enhancing processing speed.

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First Claim