Exception handling method and apparatus in data processing systems
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United States of America Patent
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Dec 23, 1997
Grant Date -
N/A
app pub date -
Aug 3, 1995
filing date -
Aug 3, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A CPU architecture is provided having a user mode (User32), a plurality of exception modes (IRQ32 etc) and a system mode (System) entered via one of the exception modes. The system mode re-uses the same set of registers (16) as the user mode and yet has access to a set of privileged resources compared to the standard resources of the user mode. Interrupt of the same type are disabled when the system is already in that exception mode, but are re-enabled when the system is moved into the system mode. Branch instructions may be used in the user and system modes, but not the exception modes.
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