Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located on a product wafer
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United States of America Patent
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Dec 30, 1997
Grant Date -
N/A
app pub date -
Apr 16, 1997
filing date -
Aug 31, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.
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