Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore
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United States of America Patent
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Dec 30, 1997
Grant Date -
N/A
app pub date -
Feb 22, 1995
filing date -
Feb 22, 1995
priority date (Note) -
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Abstract
Interchip and intrachip electrical discharge suppression connections or networks are disclosed for three-dimensional multichip semiconductor structures. The interchip suppression networks electrically intercouple the power planes of the semiconductor device chips in the structure. This, in combination with conventional intrachip suppression networks present on the external connects or input/output pins of the individual chips in the structure, provides complete power plane-to-power plane, external connect-to-power plane and external connect-to-external connect protection against electrical discharge events, such as an electrostatic discharge occurring during handling and testing of the structure. The interchip electrical discharge suppression networks can be placed on an end layer or end semiconductor chip of the three-dimensional multichip semiconductor structure and connect to individual chips in the structure via an edge surface metallization. Techniques for suppressing electrical discharges occurring during the fabrication of three-dimensional multichip semiconductor structure are also disclosed.
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