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Abstract

An error detecting apparatus for a packet exchange in which a block coding technique capable of using a data width of 16 bits while using a bus width of 24 bits is applied to drive the common bus of the packet exchange, thereby not only obtaining a bit exchange speed being double that of a triplicated common bus, but also detecting errors and correcting the detected errors. The apparatus includes a pair of encoding units each adapted to encode data of 8 bits and four code bits for an error detection, thereby generating a coded vector of 12 bits, a common bus adapted to interface the 12-bit coded vectors respectively generated from the encoding units, and a pair of decoding units adapted to share the common bus with each other, thereby respectively receiving the coded 12-bit vectors, each decoding unit extracting original 8-bit data from the received 12-bit vector, thereby detecting and correcting errors.

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First Claim