System for reducing noise coupling between digital and analog circuitry
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United States of America Patent
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Jan 6, 1998
Grant Date -
N/A
app pub date -
Sep 18, 1995
filing date -
Sep 18, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for reducing noise coupling in a mixed-signal IC includes a digital clock, an analog clock, and gating signal generator, and a gating circuit. The gating circuit receives a digital clock signal and the gating pulse to generate a gated digital clock signal having no pulses at a sampling edge of the analog clock signal to provide a 'quiet time' for analog sampling.
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