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Abstract

Atomic memory references require a data processing system to present the appearance of a coherent memory system, which may be achieved in most multiprocessor systems by means of normal memory coherency systems. Writes or attempted writes to memory must be monitored by a processor in order to correctly resolve hits against the reservation state. In a two level cache system the second level cache filters bus operations and forwards to the processor any bus traffic that may involve data stored within the first level cache. This may be accomplished by enforcing an 'inclusion' property wherein all data entries within the first level cache are required to be maintained within higher level caches. A problem arises when a block within a first level cache which has had a reservation pending is cast out and the second level cache no longer forwards bus traffic to the associated processor, despite the continued pendency of the reservation. This problem is avoided by setting a reservation flag each time a valid reservation is pending. Thereafter, any replacement of a data entry in a higher level cache results in the automatic deletion of the corresponding data entry within any included level of cache. The reservation flag is then reset in response to the occurrence of either a bus operation which affects the reservation address or the deletion of the cache data entry corresponding to the reservation address, permitting atomic memory references to be achieved without the necessity of distributing the reservation address.

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