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Abstract

A circuit contains a microprocessor die, containing a microprocessor, and a cache memory die, containing a cache memory, for operation in conjunction with the microprocessor. A microprocessor clock and a cache memory clock are generated for operation of the microprocessor and the cache memory, respectively. The microprocessor and cache memory clocks are generated on the microprocessor die, and the cache memory clock is transmitted to the cache memory die. In order to transmit data between the microprocessor die and the cache memory die, clock cycles are designated. The microprocessor clock and the cache memory clock are synchronized to the clock cycles including compensation for the propagation delay between the two dies. The microprocessor includes a stop clock function which halts the cache memory clock and the microprocessor clock on the same clock cycle so that data integrity, in both the microprocessor and cache memory, are maintained. In order to provide functional operation over a range of clock cycle frequencies, the data, from cache memory die, becomes valid on the falling edge of the cache clock signal, and is subsequently sampled, in the same clock cycle, on the rising edge of the microprocessor clock.

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First Claim