Dual bus computer architecture utilizing distributed arbitrators and method of using same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 13, 1998
Grant Date -
N/A
app pub date -
Feb 20, 1997
filing date -
Nov 27, 1991
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A dual bus architecture for a computer system including a number of computer system devices and a number of computer system resources. Each of the computer system devices and computer system resources are coupled by first and second communication busses. First and second bus arbitrators provide bus arbitration functions allowing first and second computer system devices to access first and second computer system resources simultaneously. A method of accessing a number of computer system resources by a number of computer system devices coupled by a dual bus architecture is also provided.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully