Sysem for distributing clock signals
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United States of America Patent
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Jan 27, 1998
Grant Date -
N/A
app pub date -
Dec 29, 1995
filing date -
Jun 6, 1994
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A system for convening between parallel data and serial data is described. In the system (b 10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is convened into serial data.
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