Importance

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Abstract

A microprocessor 1 is coupled to a memory 2, and includes an instruction pipeline 3 and a register file 4. The register file 4 includes an address read/write circuit 5, a plurality of frame address storing registers 6 coupled to the address read/write circuit 5, data read/write circuits 7 and 10, and register banks 8 of the same number as that of the frame address storing registers 6. The register banks 8 is coupled to the data read/write circuits 7 and 10, and all the register banks 8 are composed of the same number of registers 9. The instruction pipeline 3 is coupled to the register file 4 through a register designating bus 104, a data transfer bus 105, and an address transfer bus 106. The instruction pipeline 3 is also coupled to the memory 2 through a memory address bus 101 and an instruction supply bus 102, and the data read/write circuit 10 is coupled to the memory 2 through a data transfer bus 103. At the time of the context switching, the overhead required for the save/restore of the content stored in the register file can be reduced.

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First Claim