Method for designing an interconnection route in an LSI

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United States of America Patent

PATENT NO 5717600
SERIAL NO

08667482

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Abstract

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A method for designing an interconnection route in an LSI includes steps of finding a minimum-cost path among possible paths for a current net, the possible paths overlapping with existing nets routed before the current net. A unit cost assigned to a grid for scoring possible paths includes a length cost and a rip-up and reroute cost for ripping-up and rerouting the existing nets overlapping with the current net in the grid. The rip-up and reroute cost is not scored, however, when the existing nets also overlaps with the current net in another grid so far routed. The route will be possibly selected in a path overlapping with a several wire segments of a single existing net rather than overlapping with a single segment of each of a plurality of existing nets. Number of rip-up and reroute procedure is reduced so that the speed of routing process is improved, providing a lower cost for routing an interconnection route in a computer.

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Patent Owner(s)

  • NEC ELECTRONICS CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ishizuka, Akio Tokyo, JP 16 389

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