Multiple monolithic phase locked loops
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United States of America Patent
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Feb 10, 1998
Grant Date -
N/A
app pub date -
Dec 22, 1995
filing date -
Dec 22, 1995
priority date (Note) -
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Abstract
A monolithic device is shown having a number of phase locked loops (PLLs) constructed thereon. At least one of the PLLs is constructed as a multiple loop having an output of one PLL loop tied back to the feedback path of the other loop of the pair. In this manner, tight resolution can be obtained in one loop while the bandwidth of that loop is coarse. The bandwidth of the second loop is tight, thereby giving good resolution to the first loop while still avoiding the problems inherent with noise injection locking from other PLLs on the same device.
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