Multiple bus control method and a system thereof

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United States of America Patent

PATENT NO 5717852
SERIAL NO

08661800

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Abstract

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In the bus constitution in an information processing unit for transferring data between a bus-master and bus-slave via a plurality of buses, if a fault occurs in a bus when data is transferred between the bus-master and bus-slave via the buses and the H side fault detection/reporting circuit of the bus-slave or the H side fault detection/processing circuit of the bus-master detects the fault, the data transfer via the bus is stopped and information indicating that the bus is faulty is stored in the bus status information keeping circuit. When the data transfer via the bus ends normally thereafter, the bus selector confirms that the bus is normal from the information of the bus status information keeping circuit and activates the L side bus controller so as to operate the bus and to transfer the data which cannot be transferred due to the bus fault via the bus.

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Patent Owner(s)

Patent OwnerAddress
HITACHI LTDTOKYO 100-8280

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Izuno, Nobuaki Fukuoka, JP 3 52
Kurosu, Yasuo Yokosuka, JP 31 719

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