Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
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United States of America Patent
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Feb 10, 1998
Grant Date -
N/A
app pub date -
Mar 1, 1995
filing date -
Apr 30, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for processing data by utilizing hierarchial cache memories in a system where a lower cache is connected between a processor and a higher cache memory and the higher cache memory is in turn connected to a main memory or connected through a serial arrangement of higher cache memories to the main memory. When a cache miss occurs in the lower cache and the lower cache is full of 'dirty data', the data is not written to the main memory but instead to the higher cache. Dirty data is written into the main memory when at least all of the cache memories are filled with dirty data and a cache miss occurs.
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