Lock generator circuit for use with a dual edge register that provides a separate enable for each use of an input clock signal
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 17, 1998
Grant Date -
N/A
app pub date -
Dec 20, 1995
filing date -
Dec 20, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A clock generator circuit for providing a clock signal to a dual-edged D-type flip-flop, enabling the flip-flop to be dual edged, single edged, or to enable a user to provide clock edge selection, asynchronous clocking, clock enabling, or a mixture of different type clock signals. The clock generator circuit includes inputs receiving first and second enables signals and a clock signal. The clock generator circuit further includes circuitry to provides an output clock signal which transitions when a rising edge of a pulse of the clock signal is received when the first clock signal is enabled, or if a falling edge of a pulse of the clock signal is received when the second clock signal is enabled.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully