Memory with EEPROM cell having capacitive effect and method for the reading of such a cell
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United States of America Patent
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Feb 24, 1998
Grant Date -
N/A
app pub date -
Apr 9, 1996
filing date -
May 29, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a memory cell of an EEPROM or flash-EEPROM memory, the source and the drain of a floating-gate transistor forming the non-volatile memorizing device are connected together. It is shown that the capacitive behavior of the cell is then differentiated at the time of the reading depending on whether it is in a programmed state or in an erased state. This difference in behavior is used to differentiate the logic states.
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