Block segmentation of configuration lines for fault tolerant programmable logic device
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United States of America Patent
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Feb 24, 1998
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N/A
app pub date -
Dec 11, 1995
filing date -
Dec 11, 1995
priority date (Note) -
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Abstract
A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to each of the blocks. An independent address circuit is provided within each block. A block select line is coupled to each block such that when the block select is line is asserted the address circuit of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address circuit and data bus.
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