US Patent No: 5,721,697
Number of patents in Portfolio can not be more than 2000
Performing tree additions via multiplication
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Feb 24, 1998
Issued date -
May 17, 1996
filing date -
08/649,349
serial no -
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Abstract
A multiplier is modified to perform a tree addition. A first value is input to the multiplier in place of a first multiplicand. The first value is a concatenation of addends upon which the tree addition is performed. A second value is input into the multiplier in place of a second multiplicand. Each bit of the second value is at logic zero except for a first subset of bits. The first subset of bits are bits of the second value, starting with the low order bit, which are at intervals equal to a bit length of each addend. Each of the first subset of bits is set to logic one. In partial product rows in the multiplier which correspond to the first subset of bits, certain partial products are forced to logic zero. This is done in such a way that all the addends for the tree addition are aligned in columns of the multiplier. The partial products are then summed to produce a result.
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 4,369,500 High speed NXM bit digital, repeated addition type multiplying circuit | 22 | 1980 | |
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| 5,095,457 Digital multiplier employing CMOS transistors | 115 | 1990 | |
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| 4,736,335 Multiplier-accumulator circuit using latched sums and carries | 33 | 1984 | |