US Patent No: 5,721,697

Number of patents in Portfolio can not be more than 2000

Performing tree additions via multiplication

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A multiplier is modified to perform a tree addition. A first value is input to the multiplier in place of a first multiplicand. The first value is a concatenation of addends upon which the tree addition is performed. A second value is input into the multiplier in place of a second multiplicand. Each bit of the second value is at logic zero except for a first subset of bits. The first subset of bits are bits of the second value, starting with the low order bit, which are at intervals equal to a bit length of each addend. Each of the first subset of bits is set to logic one. In partial product rows in the multiplier which correspond to the first subset of bits, certain partial products are forced to logic zero. This is done in such a way that all the addends for the tree addition are aligned in columns of the multiplier. The partial products are then summed to produce a result.

Loading the Abstract Image... loading....

First Claim

See full text

all claims..

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.HOUSTON, TX27575

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Ruby Bei-Loh Los Altos Hills, CA 5 114

Cited Art Landscape

Patent Info (Count) # Cites Year
 
MOTOROLA, INC. (1)
4,369,500 High speed NXM bit digital, repeated addition type multiplying circuit 23 1980
 
SAMSUNG ELECTRONICS CO., LTD. (1)
5,095,457 Digital multiplier employing CMOS transistors 130 1990
 
ZORAN CORPORATION (1)
4,736,335 Multiplier-accumulator circuit using latched sums and carries 53 1984

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTEL CORPORATION (18)
6,418,529 Apparatus and method for performing intra-add operation 48 1998
6,377,970 Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry 70 1998
6,243,803 Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry 27 1998
7,516,307 Processor for computing a packed sum of absolute differences and packed multiply-add 3 2001
7,424,505 Method and apparatus for performing multiply-add operations on packed data 1 2001
6,961,845 System to perform horizontal additions 2 2002
7,430,578 Method and apparatus for performing multiply-add operations on packed byte data 37 2003
7,395,298 Method and apparatus for performing multiply-add operations on packed data 37 2003
7,395,302 Method and apparatus for performing horizontal addition and subtraction 0 2003
7,392,275 Method and apparatus for performing efficient transformations with horizontal addition and subtraction 1 2003
7,509,367 Method and apparatus for performing multiply-add operations on packed data 0 2004
8,185,571 Processor for performing multiply-add operations on packed data 1 2009
8,626,814 Method and apparatus for performing multiply-add operations on packed data 0 2011
8,725,787 Processor for performing multiply-add operations on packed data 0 2012
8,396,915 Processor for performing multiply-add operations on packed data 3 2012
8,495,123 Processor for performing multiply-add operations on packed data 0 2012
8,793,299 Processor for performing multiply-add operations on packed data 0 2013
8,745,119 Processor for performing multiply-add operations on packed data 0 2013