Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready
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United States of America Patent
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Feb 24, 1998
Grant Date -
N/A
app pub date -
Apr 3, 1996
filing date -
Mar 30, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.
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