Fabrication procedure for a stable post

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United States of America Patent

PATENT NO 5722162
SERIAL NO

08541219

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beilin, Solomon I San Carlos, CA 53 3555
Chou, William T Cupertino, CA 29 1262
Horine, David A Los Altos, CA 23 890
Kudzuma, David San Jose, CA 9 599
Lee, Michael G San Jose, CA 77 2750
Moresco, Larry Louis San Carlos, CA 7 306
Wang, Wen-chou Vincent Cupertino, CA 45 2530

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