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Abstract

An n:1 time division multiplexer includes a multiphase clock generator, a data multiplexer, a reference multiplexer, a reference generator and a comparison circuit. The multiphase clock generator has a plurality of select clock outputs with different phases. The data multiplexer has a plurality of data inputs, a plurality of select clock inputs and a data output. The select clock inputs of the data multiplexer are coupled to corresponding select clock outputs. The reference multiplexer has a plurality of reference data inputs, a plurality of select clock inputs and a first reference output. The select clock inputs of the reference multiplexer are coupled to corresponding select clock outputs. The reference generator has a second reference output. The comparison circuit has first and second comparison inputs coupled to the first and second reference outputs, respectively, and has a comparison output coupled to the plurality of select clock outputs. The comparison output adjusts an overlap between each pair of select clock outputs that are substantially 180 degrees apart in phase as a function of a comparison between the output characteristics of the first and second reference outputs.

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