Interface for connecting a bus to a random access memory using a two wire link
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United States of America Patent
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Mar 3, 1998
Grant Date -
N/A
app pub date -
Mar 6, 1997
filing date -
Mar 24, 1994
priority date (Note) -
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Abstract
The invention provides a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The interface utilizes a plurality of swing buffers, and has a control module for coordinating accesses thereto, which is connected to the address generator by a specialized two-wire interface. The address generator and the source of data are clocked asynchronously and at different clock rates.
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