US Patent No: 5,726,588
Number of patents in Portfolio can not be more than 2000
Differential-to-CMOS level converter having cross-over voltage adjustment
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Mar 10, 1998
Issued date -
Aug 15, 1996
filing date -
08/698,306
serial no -
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Abstract
A differential-to-CMOS level converter includes a differential-to-CMOS conversion circuit, first and second buffers and a cross-over adjustment circuit. The conversion circuit has first and second differential input terminals and first and second complementary output terminals. The first buffer has a buffer input coupled to the first complementary output and has a buffer output. The second buffer has a buffer input coupled to the second complementary output and has a buffer output. The cross-over adjustment circuit has first and second voltage measurement inputs coupled to the first and second buffer outputs and has first and second offset current outputs coupled to the first and second buffer inputs, respectively.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 4,965,797 Parallel-to-serial converter | 19 | 1989 | |
| 5,585,743 ECL-CMOS level conversion circuit | 5 | 1995 | |
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| 5,463,630 Method of converting a parallel, time-division multiplexed data stream into individual serial data streams and vice versa, and converter therefor | 20 | 1994 | |
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| 4,445,215 Programmable frequency ratio synchronous parallel-to-serial data converter | 19 | 1982 | |
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| 5,606,268 Differential to single-ended CMOS converter | 52 | 1995 | |
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| 5,526,360 High speed N-to-1 burst time-multiplexed data transmission system and method | 16 | 1995 | |
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| 5,426,381 Latching ECL to CMOS input buffer circuit | 10 | 1994 | |
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| 5,025,257 Increased performance of digital integrated circuits by processing with multiple-bit-width digits | 10 | 1990 | |
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| 5,349,653 Apparatus for converting parallel bits of an electrical data signal into serial bits of an optical data signal utilizing an optical time delay | 6 | 1991 | |
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| 5,175,819 Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer | 67 | 1990 | |
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| 4,750,149 Programmable FIFO buffer | 29 | 1986 | |
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| 4,901,076 Circuit for converting between serial and parallel data streams by high speed addressing | 33 | 1987 | |
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| 5,614,843 CMOS-PECL level conversion circuit | 10 | 1996 | |
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| 5,247,652 Parallel to serial converter enabling operation at a high bit rate with slow components by latching sets of pulses following sequential delays equal to clock period | 21 | 1990 | |
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| 5,317,214 Interface circuit having differential signal common mode shifting means | 13 | 1993 | |
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| 5,548,241 Voltage reference circuit using an offset compensating current source | 9 | 1994 | |
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| 4,728,930 Parallel-to-serial-data interface-adaptor | 30 | 1987 | |
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| 5,182,467 High performance multiplexer for improving bit error rate | 17 | 1991 | |