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Abstract

A multiplexer includes an n-th stage as a final output stage (n=integer, 2.ltoreq.n); j stages (j=integer, 1.ltoreq.j.ltoreq.n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m.sup.n-j-1 (m=integer, 2.ltoreq.m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit vary due to device parameters or temperature, the timing of the data input can be adjusted by the variable delay circuit.

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