Method for shallow trench isolation

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United States of America Patent

PATENT NO 5728621
SERIAL NO

08845870

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Abstract

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A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height. A layer of spin-on-glass is coated over the HDP oxide layer wherein the difference in step heights of the spin-on-glass material between the first region and the region overlying an isolation trench is a second height smaller than the first height. The spin-on-glass layer and portions of the HDP oxide layer in the first region are etched away. The spin-on-glass layer and HDP oxide layer remaining are polished away wherein the substrate is planarized.

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Patent Owner(s)

Patent OwnerAddress
CHARTERED SEMICONDUCTOR MANUFACTURING PTE LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 738406

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Lap San Francisco, CA 159 4868
Lu, Wei Singapore, SG 656 6848
Tay, Charlie Wee Song Johor, MY 1 112
Zheng, Jia Zhen Singapore, SG 96 1945

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