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Abstract

An improved memory controller of a computer system is described. The computer system includes a microprocessor and a memory coupled to the memory controller that controls access to the memory. An interface circuit is coupled to the microprocessor for receiving a first address to access the memory. The memory includes a first memory bank and a second memory bank. A memory control circuit is coupled to the interface circuit for generating control signals to access the memory. An address generation circuit is coupled to receive the first address from the interface circuit for generating a first memory address and a second memory address in accordance with the first address to access the memory during a burst access to the memory from the microprocessor. The address generation circuit further comprises circuitry for generating and applying the first memory address sequentially to the first and second memory banks and circuitry for generating and applying the second memory address sequentially to the first and second memory banks. The second memory address is generated by inverting at least the lowest order address bit in the first memory address Access time of the burst access is minimized by using the first microprocessor memory address and generating a second memory address therefrom.

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First Claim