
US Patent No: 5,729,894
Number of patents in Portfolio can not be more than 2000
Method of assembling ball bump grid array semiconductor packages
Stats
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Mar 24, 1998
Issued date -
Jun 14, 1996
filing date -
08/664,146
serial no -
In Force
status
Importance
Abstract
A ball bump grid array package includes dies on one surface of a printed wiring board (PWB) and an array of ball bumps on the other surface of the PWB. The die is interconnected with the ball bumps by bond wires, traces on the one surface of the PWB, vias through the PWB and traces on the other surface of the PWB. Various die encapsulation schemes are discussed. The PWB is formed of FR4, BT, teflon or polyimide, or ceramic materials. The die may be connected to the traces on the one surface of the PWB with solder balls, rather than with bond wires. Two or more dies may be disposed on the one surface of the PWB, within the plastic molded body. The ball bumps on the other surface of the PWB may be arranged in a multiple grid pitch array--ball bumps within a central area being on a first pitch, and ball bumps without the central area being on a second pitch which is a multiple of the first pitch.
First Claim
Related Publications
International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 5,216,278 Semiconductor device having a pad array carrier package | 519 | 1992 | |
| 5,334,857 Semiconductor device with test-only contacts and method for making the same | 113 | 1992 | |
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| 4,975,765 Highly integrated circuit and method for the production thereof | 74 | 1989 | |
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| 4,539,622 Hybrid integrated circuit device | 42 | 1984 | |
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| 4,628,406 Method of packaging integrated circuit chips, and integrated circuit package | 70 | 1985 | |