US Patent No: 5,729,894

Number of patents in Portfolio can not be more than 2000

Method of assembling ball bump grid array semiconductor packages

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ATTORNEY / AGENT: (SPONSORED)
 

Importance

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Abstract

A ball bump grid array package includes dies on one surface of a printed wiring board (PWB) and an array of ball bumps on the other surface of the PWB. The die is interconnected with the ball bumps by bond wires, traces on the one surface of the PWB, vias through the PWB and traces on the other surface of the PWB. Various die encapsulation schemes are discussed. The PWB is formed of FR4, BT, teflon or polyimide, or ceramic materials. The die may be connected to the traces on the one surface of the PWB with solder balls, rather than with bond wires. Two or more dies may be disposed on the one surface of the PWB, within the plastic molded body. The ball bumps on the other surface of the PWB may be arranged in a multiple grid pitch array--ball bumps within a central area being on a first pitch, and ball bumps without the central area being on a second pitch which is a multiple of the first pitch.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
LSI LOGIC CORPORATIONMILPITAS, CA4131

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fulcher, Edwin Palo Alto, CA 4 448
Rostoker, Michael D Boulder Creek, CA 204 9991
Schneider, Mark R Williston, VT 31 620

Cited Art

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Patent Citation Ranking

Forward Cites

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