Importance

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Abstract

Disclosed is a die structure which allows some or all routing to be performed in an integrated circuit packaging substrate (e.g., a package or circuit board). The packaging substrate acts as one or more interconnect levels. The die and packaging substrate arrangement takes the form of a flip chip design in which multiple solder bumps are formed on an active surface of the die. The active surface is largely or fully 'populated' with such solder bumps to allow electrical connection to the packaging substrate at many different sites, depending upon the specific design employed. The solder bumps are electrically connected to various device elements or circuit components on the die itself. In this manner, many different integrated circuit designs may be implemented with the die (in the manner of a gate array) by employing different routing arrangements in the packaging substrate and allowing contact with subsets of the solder pad array.

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First Claim