Multi-function microprocessor wait state mechanism using external control line
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United States of America Patent
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Mar 24, 1998
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N/A
app pub date -
Jan 20, 1997
filing date -
Sep 15, 1994
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Abstract
A wait state mechanism for lengthening a microprocessor's bus cycle to allow data transfers between slower off-chip devices. A microprocessor is responsive to a bus control signal generated by external programmable logic which instructs the microprocessor to insert wait states of varying number depending on the component involved in a bus transaction. The microprocessor receives only a single input from the programmable logic and varies its bus cycle length accordingly.
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