
US Patent No: 5,734,581
Number of patents in Portfolio can not be more than 2000
Method for implementing tri-state nets in a logic emulation system
Stats
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Mar 31, 1998
Issued date -
Dec 19, 1996
filing date -
08/769,659
serial no -
In Force
status
Importance
Abstract
A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERQGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
First Claim
Related Publications
International Classification(s)
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- [Patents Count]
Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 4,306,286 Logic simulation machine | 172 | 1979 | |
| 4,386,403 System and method for LSI circuit analysis | 47 | 1979 | |
| 4,503,386 Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks | 63 | 1982 | |
| 4,656,580 Logic simulation machine | 111 | 1982 | |
| 4,593,363 Simultaneous placement and wiring for VLSI chips | 152 | 1983 | |
| 4,862,347 System for simulating memory arrays in a logic simulation machine | 102 | 1986 | |
| 4,695,999 Cross-point switch of multiple autonomous planes | 64 | 1986 | |
| 4,849,904 Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices | 53 | 1987 | |
| 5,003,487 Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis | 91 | 1988 | |
| 5,263,149 Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles | 36 | 1991 | |
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| 4,541,071 Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates | 41 | 1983 | |
| 4,752,887 Routing method for use in wiring design | 71 | 1986 | |
| 4,747,102 Method of controlling a logical simulation at a high speed | 32 | 1986 | |
| 4,945,503 Hardware simulator capable of reducing an amount of information | 42 | 1987 | |
| 4,924,429 Hardware logic simulator | 50 | 1988 | |
| 5,041,986 Logic synthesis system comprising a memory for a reduced number of translation rules | 32 | 1989 | |
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| 4,642,487 Special interconnect for configurable logic array | 396 | 1984 | |
| 4,706,216 Configurable logic element | 473 | 1985 | |
| 4,758,985 Microprocessor oriented configurable logic element | 252 | 1986 | |
| 4,870,302 Configurable electrical circuit having configurable logic elements and configurable interconnects | 682 | 1988 | |
| 5,343,406 Distributed memory architecture for a configurable logic array and method for using distributed memory | 237 | 1989 | |
| 5,224,056 Logic placement using positionally asymmetrical partitioning algorithm | 124 | 1991 | |
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|
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| 4,787,061 Dual delay mode pipelined logic simulator | 55 | 1986 | |
| 4,736,338 Programmable look up system | 31 | 1986 | |
| 4,744,084 Hardware modeling system and method for simulating portions of electrical circuits | 129 | 1987 | |
| 5,377,124 Field programmable printed circuit board | 45 | 1989 | |
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|
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| 4,578,761 Separating an equivalent circuit into components to detect terminating networks | 30 | 1983 | |
| 4,577,276 Placement of components on circuit substrates | 118 | 1983 | |
| 4,908,772 Integrated circuits with component placement by rectilinear partitioning | 135 | 1987 | |
|
|
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| 4,942,536 Method of automatic circuit translation | 56 | 1986 | |
| 4,803,636 Circuit translator | 54 | 1986 | |
| 5,046,017 Wiring design for semiconductor integrated circuit | 58 | 1988 | |
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| 5,233,539 Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | 152 | 1989 | |
| 5,260,881 Programmable gate array with improved configurable logic block | 73 | 1989 | |
| 5,231,588 Programmable gate array with logic cells having symmetrical input/output structures | 100 | 1990 | |
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|
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| 4,697,241 Hardware logic simulator | 105 | 1985 | |
| 4,914,612 Massively distributed simulation engine | 78 | 1988 | |
| 5,109,353 Apparatus for emulation of electronic hardware system | 177 | 1988 | |
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| 4,700,187 Programmable, asynchronous logic cell and array | 138 | 1985 | |
| 4,918,440 Programmable logic cell and array | 153 | 1986 | |
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| 4,942,615 Gate processor arrangement for simulation processor system | 38 | 1988 | |
| 5,258,932 PLA simulation method | 24 | 1991 | |
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| 4,918,594 Method and system for logical simulation of information processing system including logic circuit model and logic function model | 53 | 1987 | |
| 5,231,589 Input/output pin assignment method | 34 | 1990 | |
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| 4,835,705 Interconnection area decision processor | 53 | 1987 | |
| 4,876,466 Programmable logic array having a changeable logic structure | 107 | 1988 | |
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| 5,081,602 Computer simulator for electrical connectors | 34 | 1989 | |
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|
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| 5,093,920 Programmable processing elements interconnected by a communication network including field operation unit for performing field operations | 46 | 1989 | |
|
|
|||
| 4,949,275 Semiconductor integrated circuit device made by a standard-cell system and method for manufacture of same | 52 | 1985 | |
|
|
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| 4,931,946 Programmable tiles | 50 | 1988 | |
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|
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| 4,621,339 SIMD machine using cube connected cycles network architecture for vector processing | 157 | 1983 | |
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| 4,935,734 Semi-conductor integrated circuits/systems | 145 | 1986 | |
|
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| 2002/0186,837 Multiple prime number generation using a parallel prime number search algorithm | 2001 | ||
|
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| 4,882,690 Incremental logic synthesis method | 81 | 1986 | |
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| 5,023,775 Software programmable logic array utilizing "and" and "or" gates | 105 | 1990 | |
|
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| 4,722,084 Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits | 61 | 1985 | |
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| 4,823,276 Computer-aided automatic wiring method for semiconductor integrated circuit device | 48 | 1987 | |
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| 5,253,181 Programmable one-board computer, and methods of verification of logic circuit and alteration to actual circuit using the programmable one-board computer | 41 | 1990 | |
|
|
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| 4,901,259 Asic emulator | 82 | 1988 | |
|
|
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| 4,791,602 Soft programmable logic array | 60 | 1986 | |
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|
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| 5,053,980 Method and apparatus for logic simulation | 35 | 1989 | |
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| 5,084,824 Simulation model generation from a physical data base of a combinatorial circuit | 137 | 1990 | |
|
|
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| 4,901,260 Bounded lag distributed discrete event simulation method and apparatus | 65 | 1987 | |
|
|
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| 4,777,606 Method for deriving an interconnection route between elements in an interconnection medium | 142 | 1986 | |
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| 5,452,227 Method and apparatus for converting a programmable logic device designed into a selectable target gate array design | 51 | 1991 | |
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| 4,811,214 Multinode reconfigurable pipeline computer | 211 | 1986 | |
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| 4,768,196 Programmable logic array | 54 | 1986 | |
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| 4,612,618 Hierarchical, computerized design of integrated circuits | 106 | 1983 | |
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| 4,815,003 Structured design method for high density standard cell and macrocell layout of VLSI chips | 143 | 1987 | |
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|
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| 4,922,432 Knowledge based method and apparatus for designing integrated circuits using functional specifications | 169 | 1988 | |
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| 4,488,354 Method for simulating and testing an integrated circuit chip | 61 | 1981 | |
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| 4,951,220 Method and apparatus for manufacturing a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems | 38 | 1988 | |
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| 4,740,919 Electrically programmable logic array | 35 | 1986 | |
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| 4,656,592 Very large scale integrated circuit subdivided into isochronous regions, method for the machine-aided design of such a circuit, and method for the machine-aided testing of such a circuit | 101 | 1984 | |
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| 4,675,832 Visual display logic simulation system | 75 | 1984 | |
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| 4,965,739 Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected | 76 | 1989 | |
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| 4,786,904 Electronically programmable gate array having programmable interconnect lines | 166 | 1986 | |
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| 4,682,440 Animal trap | 28 | 1986 | |
| 4,849,928 Logic array programmer | 41 | 1987 | |
| 4,827,427 Instantaneous incremental compiler for producing logic circuit designs | 101 | 1987 | |
| 5,051,938 Simulation of selected logic circuit designs | 118 | 1989 | |