US Patent No: 5,734,581

Number of patents in Portfolio can not be more than 2000

Method for implementing tri-state nets in a logic emulation system

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Abstract

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A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERQGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
QUICKTURN DESIGN SYSTEMS, INC.SAN JOSE, CA10

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Batcheller, Jon A Newberg, OR 10 845
Butts, Michael R Portland, OR 48 1913

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (8)
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* 4,862,347 System for simulating memory arrays in a logic simulation machine 126 1986
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* 4,849,904 Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices 54 1987
* 5,003,487 Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis 93 1988
* 5,263,149 Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles 37 1991
 
NEC CORPORATION (6)
* 4,541,071 Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates 41 1983
* 4,752,887 Routing method for use in wiring design 71 1986
* 4,747,102 Method of controlling a logical simulation at a high speed 32 1986
* 4,945,503 Hardware simulator capable of reducing an amount of information 42 1987
* 4,924,429 Hardware logic simulator 50 1988
* 5,041,986 Logic synthesis system comprising a memory for a reduced number of translation rules 32 1989
 
XILINX, INC. (6)
* 4,642,487 Special interconnect for configurable logic array 407 1984
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* 4,758,985 Microprocessor oriented configurable logic element 263 1986
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* 5,343,406 Distributed memory architecture for a configurable logic array and method for using distributed memory 260 1989
* 5,224,056 Logic placement using positionally asymmetrical partitioning algorithm 125 1991
 
MENTOR GRAPHICS CORPORATION (4)
* 4,787,061 Dual delay mode pipelined logic simulator 55 1986
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Bell Telephone Laboratories, Incorporated (3)
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HITACHI MICROCOMPUTER ENGINEERING LTD. (3)
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* 4,803,636 Circuit translator 54 1986
* 5,046,017 Wiring design for semiconductor integrated circuit 58 1988
 
LATTICE SEMICONDUCTOR CORPORATION (3)
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* 5,260,881 Programmable gate array with improved configurable logic block 73 1989
* 5,231,588 Programmable gate array with logic cells having symmetrical input/output structures 104 1990
 
QUICKTURN DESIGN SYSTEMS, INC. (3)
* 4,697,241 Hardware logic simulator 107 1985
* 4,914,612 Massively distributed simulation engine 80 1988
* 5,109,353 Apparatus for emulation of electronic hardware system 184 1988
 
ATMEL CORPORATION (2)
* 4,700,187 Programmable, asynchronous logic cell and array 142 1985
* 4,918,440 Programmable logic cell and array 166 1986
 
FUJITSU LIMITED (2)
* 4,942,615 Gate processor arrangement for simulation processor system 38 1988
* 5,258,932 PLA simulation method 25 1991
 
HITACHI, LTD. (2)
* 4,918,594 Method and system for logical simulation of information processing system including logic circuit model and logic function model 53 1987
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MITSUBISHI DENKI KABUSHIKI KAISHA (2)
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AMP Incorporated (1)
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AT&T Bell Laboratories (1)
* 5,093,920 Programmable processing elements interconnected by a communication network including field operation unit for performing field operations 47 1989
 
BANK SOUTH, N.A. (1)
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CIRRUS LOGIC INTERNATIONAL LTD. (1)
* 4,931,946 Programmable tiles 50 1988
 
DUKE UNIVERSITY (1)
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FREESCALE SEMICONDUCTOR, INC. (1)
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HITACHI SOFTWARE ENGINEERING CO., LTD. (1)
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INTEL CORPORATION (1)
* 5,023,775 Software programmable logic array utilizing "and" and "or" gates 118 1990
 
ITT CORPORATION (1)
* 4,722,084 Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits 61 1985
 
KABUSHIKI KAISHA TOSHIBA (1)
* 4,823,276 Computer-aided automatic wiring method for semiconductor integrated circuit device 49 1987
 
KAWASAKI MICROELECTRONICS, INC. (1)
* 5,253,181 Programmable one-board computer, and methods of verification of logic circuit and alteration to actual circuit using the programmable one-board computer 42 1990
 
LSI LOGIC CORPORATION (1)
* 4,901,259 Asic emulator 83 1988
 
MARHOEFER, LAURENCE J. (1)
* 4,791,602 Soft programmable logic array 60 1986
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
* 5,053,980 Method and apparatus for logic simulation 35 1989
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
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NCR CORPORATION (1)
* 4,901,260 Bounded lag distributed discrete event simulation method and apparatus 65 1987
 
NORTEL NETWORKS LIMITED (1)
* 4,777,606 Method for deriving an interconnection route between elements in an interconnection medium 146 1986
 
NORTHROP GRUMMAN CORPORATION (1)
* 5,452,227 Method and apparatus for converting a programmable logic device designed into a selectable target gate array design 51 1991
 
PRINCETON UNIVERSITY, NON-PROFIT ORGANIZATION (1)
* 4,811,214 Multinode reconfigurable pipeline computer 235 1986
 
RACAL RESEARCH INC. (1)
* 4,768,196 Programmable logic array 54 1986
 
RCA Corporation (1)
* 4,612,618 Hierarchical, computerized design of integrated circuits 107 1983
 
RICA CORPORATION, A CORP. OF DE (1)
* 4,815,003 Structured design method for high density standard cell and macrocell layout of VLSI chips 149 1987
 
RICOH COMPANY, LTD. (1)
* 4,922,432 Knowledge based method and apparatus for designing integrated circuits using functional specifications 170 1988
 
SAMSUNG ELECTRONICS CO., LTD. (1)
* 4,488,354 Method for simulating and testing an integrated circuit chip 61 1981
 
SHIELDIP, INC. (1)
* 2004/0133,803 Methods and apparatus for protecting information 5 2003
 
SIEMENS AKTIENGESELLSCHAFT (1)
* 4,951,220 Method and apparatus for manufacturing a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems 50 1988
 
TEXAS INSTRUMENTS INCORPORATED (1)
* 4,740,919 Electrically programmable logic array 35 1986
 
U.S. PHILIPS CORPORATION (1)
* 4,656,592 Very large scale integrated circuit subdivided into isochronous regions, method for the machine-aided design of such a circuit, and method for the machine-aided testing of such a circuit 106 1984
 
United Kingdom and British Telecommunications (1)
* 4,675,832 Visual display logic simulation system 75 1984
 
VLSI TECHNOLOGY, INC. (1)
* 4,965,739 Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected 80 1989
 
ZORAN CORPORATION (1)
* 4,786,904 Electronically programmable gate array having programmable interconnect lines 167 1986
 
Other [Check patent profile for assignment information] (4)
* 4,682,440 Animal trap 29 1986
* 4,849,928 Logic array programmer 42 1987
* 4,827,427 Instantaneous incremental compiler for producing logic circuit designs 101 1987
* 5,051,938 Simulation of selected logic circuit designs 119 1989
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
XILINX, INC. (4)
* 7,024,651 Partial reconfiguration of a programmable gate array using a bus macro 7 2002
7,669,163 Partial configuration of a programmable gate array using a bus macro and coupling the third design 1 2006
7,478,357 Versatile bus interface macro for dynamically reconfigurable designs 4 2006
7,619,442 Versatile bus interface macro for dynamically reconfigurable designs 0 2008
 
CADENCE DESIGN SYSTEMS, INC. (3)
6,618,698 Clustered processors in an emulation engine 42 1999
* 7,739,097 Emulation system with time-multiplexed interconnect 11 2002
7,047,179 Clustered processors in an emulation engine 2 2003
 
INTELLECTUAL VENTURES I LLC (2)
* 7,161,385 Circuit elements and parallel computational networks with logically entangled terminals 2 2004
RE43514 Circuit elements and parallel computational networks with logically entangled terminals 0 2009
 
SRC COMPUTERS, LLC (2)
7,155,602 Interface for integrating reconfigurable processors into a general purpose computing system 13 2001
7,167,976 Interface for integrating reconfigurable processors into a general purpose computing system 3 2005
 
GOOGLE INC. (1)
* 7,337,103 Method and apparatus for the automatic correction of faulty wires in a logic simulation hardware emulator / accelerator 0 2004
 
INTEL CORPORATION (1)
* 7,130,784 Logic simulation 0 2001
 
LIGA SYSTEMS, INC. (1)
7,444,276 Hardware acceleration system for logic simulation using shift register as local cache 4 2005
 
MENTOR GRAPHICS CORPORATION (1)
* 6,920,597 Uniform testing of tristate nets in logic BIST 5 2002
 
NUMERATE, INC. (1)
7,577,553 Method and apparatus for molecular mechanics analysis of molecular systems 0 2003
 
SYNOPSYS, INC. (1)
* 6,051,031 Module-based logic architecture and design flow for VLSI implementation 19 1997
 
TEXAS INSTRUMENTS INCORPORATED (1)
* 6,928,403 Automatic detection of connectivity between an emulator and a target device 2 2001
 
Other [Check patent profile for assignment information] (1)
6,263,484 Prototyping system and a method of operating the same 57 1998
* Cited By Examiner