MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin
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United States of America Patent
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Mar 31, 1998
Issued Date -
N/A
app pub date -
Nov 22, 1996
filing date -
Sep 11, 1992
priority date (Note) -
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Abstract
An object of the present invention is to provide a MOS static RAM in which the power consumption can be reduced when it is required to reduce the power consumption during standby, and sufficient soft error resistance can be secured when it is required to provide sufficient soft error resistance for the cell. A MOS static RAM of the present invention comprises a power supply circuit for generating a plurality of voltages of different voltage values and a selection circuit for selecting one voltage from among the plurality of voltages output from the power supply circuit and supplying the selected voltage as a cell data retention voltage to a flip-flop that forms a cell.
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