Method and apparatus for extracting a gate modeled circuit from a fet modeled circuit
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United States of America Patent
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Mar 31, 1998
Grant Date -
N/A
app pub date -
Dec 1, 1995
filing date -
Dec 1, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of extracting a gate model from a fet model using a computer implemented expert system apparatus to perform the steps of recognizing power, ground and clock signals; recognizing inverters; recognizing and preserving all logic signals of the fet modeled circuit; building one or more structurally based boolean partial trees for each of the recognized logic signals; heuristically pruning the one or more boolean trees; and building logic equations from the one or more boolean partial trees. The expert system apparatus comprises a fet modeled input netlist, an inference engine, a rule base, a user input, and a gate modeled output netlist.
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