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Abstract

A logic circuit simulator includes a set of programmable logic devices (PLDs) having input/output terminals connected to a hold and switch (HAS) device via a parallel bus. Each PLD includes an addressable input register for receiving and storing input data conveyed on the parallel bus and an addressable output buffer for placing its output data on the parallel bus. On each pulse of an input design clock signal each PLD simulates a separate portion of the logic, producing each bit of its output data as a logical combination of bits of its stored input data. Between design clock pulses, the HAS device successively acquires output data produced by the PLDs, rearranges the PLD output data to produce new input data for each PLD, and then successively transmits the new PLD input data words to the appropriate PLDs for storage in their input registers. The process is repeated for each cycle of the design clock signal.

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First Claim