Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns
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United States of America Patent
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Mar 31, 1998
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N/A
app pub date -
Sep 19, 1996
filing date -
Sep 9, 1992
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Abstract
Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
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