Method for in-chip testing of digital circuits of a synchronously sampled data detection channel
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United States of America Patent
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Apr 7, 1998
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N/A
app pub date -
May 31, 1996
filing date -
May 31, 1996
priority date (Note) -
Expired
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Abstract
An on-chip self-test circuit for testing digital elements of a synchronous sampling data detection channel chip, such as a PRML channel of a hard disk drive, with digital pseudo samples representative of samples coming from an analog channel section, includes a sample generator generating idealized digital pseudo samples in accordance with a predetermined spectrum response, a digital noise generator generating digital noise values, a first combining circuit combining the idealized digital pseudo samples with the digital noise values to produce noisy pseudo samples, a bias injection circuit connected to the sample generator and adding a predetermined bias to the idealized digital pseudo samples to produce biased pseudo samples, and a second combining circuit for combining the noisy pseudo samples with the biased pseudo samples to put out biased noisy pseudo samples to test digital data processing and channel control elements of the channel chip.
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