Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
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United States of America Patent
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Apr 7, 1998
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N/A
app pub date -
Sep 30, 1996
filing date -
Nov 3, 1989
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Abstract
A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
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