Importance

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Abstract

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources. A condition code register is coupled to instruction fetching resources, and connected to receive condition codes from both the defined execution unit and from the programmable execution unit. The programmable execution unit includes logic to signal the instruction fetching resources to provide a next instruction when execution of the programmed instruction is done. Resources for accessing the configuration store to program the programmable execution unit are provided, which can utilize the internal buses of the data processor or be completely independent of them.

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First Claim