Cache tag system for use with multiple processors including the most recently requested processor identification
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United States of America Patent
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Apr 7, 1998
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N/A
app pub date -
Jan 23, 1997
filing date -
May 3, 1994
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Abstract
A shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories. The main memory controller for each main memory of the system maintains a duplicate cache tag array containing current information on the status of data lines from the main memory that are stored in the cache memories. Thus, coherency checks can be performed directly by the main memory controller. This eliminates the need for each processor having a cache memory to perform a separate coherency check and to communicate the results of its coherency checks to the main memory controller, and thereby reduces delays associated with processing coherent transactions.
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